The present invention relates most generally to semiconductor devices and methods for forming the same. More particularly, the present invention is directed to the substrates upon which semiconductor devices are formed, and methods for manufacturing semiconductor devices.
The semiconductor manufacturing industry is a wafer-based manufacturing industry. That is, the substrates upon which semiconductor devices are formed, are most commonly substrates formed of semiconductor materials and which are generally flat and round and have a multiplicity of square or rectangular-shaped semiconductor devices formed thereon. These substrates, typically referred to as wafers, may include dozens, hundreds or even thousands of individual semiconductor devices which are also known as chips. In today""s semiconductor manufacturing industry, the trend is towards the use of increasingly larger wafers, typically silicon wafers. The use of larger substrates allows more devices to be simultaneously formed on the substrates. However, the wafer-based manufacturing model includes several shortcomings which are exacerbated by the increasingly larger wafer sizes.
An example of such a shortcoming is wafer cost. Silicon wafers are formed from monocrystalline silicon ingots having diameters at least as large as the desired silicon wafer. The silicon wafers are formed by slicing the hardened, crystalline ingot. As such, it can be seen that as wafer size increases, cost increases. In fact, because useful portions of the ingot must be single crystal and defect-free, costs increase exponentially with diameter.
Wafers which are typically used as substrates are essentially single crystal pieces of silicon aligned with the normal direction of the wafer surface equal to the  less than 100 greater than  direction of the crystalline lattice and the transverse and rolling directions equal to the  less than 010 greater than  and  less than 001 greater than  directions. Single crystal ingots extremely hard to grow to larger sizes and the movement to larger sized wafer diameters increases the cost of the wafers tremendously. Moreover, there are additional problems associated with the uniformity of the wafers, and strains within the lattice present another problem which becomes more and more prevalent as the size of the wafer increases. A wafer with a strained lattice is susceptible to breaking.
Another shortcoming associated with conventional wafer manufacturing, and intensified by the use of increasingly larger wafers, is the new tooling cost associated with fabricating semiconductor devices on each next-generation, larger diameter wafer substrates. New equipment must be purchased or existing equipment retrofitted to accommodate handling and processing the wafers when the next wave of larger wafers is introduced. In many cases, processing equipment which is being used within a semiconductor fabrication facility is not capable of being retrofitted to accommodate wafers which exceed a certain size. For example, a processing tool originally designed to accommodate 6xe2x80x3 diameter silicon wafers, and which has successfully been retrofitted to accommodate 8xe2x80x3 diameter silicon wafers, may not be capable of being further retrofitted to accommodate 10 or 12 inch diameter silicon wafers, because of limitations of the system hardware. Such a tool therefore becomes obsolete, and a replacement tool capable of accommodating 12xe2x80x3 wafers, must be purchased anew.
Another shortcoming associated with the use of increasingly larger substrates is the average cost necessary to produce a functional device. If a substrate, commonly a silicon wafer, is mishandled and becomes damaged, for example if it breaks, the entire wafer must be scrapped because a damaged wafer cannot be handled using processing equipment configured only for handling a standard sized undamaged wafer. Furthermore, once a wafer is cracked or chipped, it is prone to further fracturing or shattering at elevated temperatures. Once a wafer fractures or shatters, wafer fragments from the broken substrate may contaminate several other wafers, causing them to be scrapped also. Therefore, once a wafer is chipped, the entire wafer must be scrapped. As such, when a wafer is scrapped, many good devices or potentially good devices are also scrapped. When a wafer is scrapped, dozens, hundreds, or even thousands of individual semiconductor devices may be scrapped depending on the size of the substrate and the semiconductor devices.
During the semiconductor manufacturing process, several in-line monitoring techniques are carried out to assure that the physical dimensions and measurable parameters of various device features, are within the acceptable, or specified, limits. The monitoring techniques may be carried out using an active (or, xe2x80x9cproductionxe2x80x9d) device or they may be carried out upon a specially included test monitor which may be included among hundreds of active devices on a wafer. At any rate, the entire wafer must be removed from the manufacturing sequence and introduced to the analytical equipment. From a yield perspective, in-line monitoring (metrology, for example) exposes all of the chips on a wafer to the diagnostic technique thereby increasing the number of steps in the process flow through which the wafer must be processed. As the number of steps in the process flow increases, production costs increase, and the likelihood of wafer contamination or other defects, also increases.
Much of the analytical and diagnostic monitoring carried out during the fabrication sequence, occurs either outside of the manufacturing, or fabrication area or requires the destruction of the entire wafer, or both. When a wafer is removed from the controlled, xe2x80x9cclean roomxe2x80x9d environment of the fabrication area to be analyzed at various points in the manufacturing process, it is exposed to the foreign contamination of the outside environment, and the entire wafer must be scrapped. This is true even though only a single active device or test chip is being monitored on the wafer which contains hundreds of active devices. In this manner, many potentially functional devices are lost. Many of the techniques used for analytical monitoring, such as secondary ion mass spectrometry, focused ion beam spectroscopy. Auger electron spectroscopy and other SEM (scanning electron microscopic) techniques, require the wafer to be cleaved so that a small part of the wafer can be mounted within the analytical tool. As such, the entire wafer must be scrapped. It can be understood that, with increasing wafer size, a greater number of potentially good devices are sacrificed in order to carry out in-line monitoring and analytical techniques.
Moreover, the number of wafers sampled to monitor a particular processing operation is increased when a wafer-by-wafer processing operation is used. Multiple wafers must be analyzed to understand process variations from the beginning to the end of a xe2x80x9crunxe2x80x9d. This compounds the number of potentially good devices which must be sacrificed for analytical purposes.
It can be seen that there is a need to reduce the costs associated with using increasingly large semiconductor substrates, while still processing a maximum number of chips through the various processing operations and producing a maximum number of functional devices.
The present invention provides a modular substrate-based manufacturing model for the semiconductor manufacturing industry and represents a move away from the wafer-based model and the trend towards wafers of increasingly larger size. More specifically, the present invention provides multiple modular semiconductor processing units which can be individually or sequentially processed in state-of-the-art semiconductor processing equipment, to produce devices having sub-micron features at the leading edge of technology. The modular processing units each contain at least one die or semiconductor device. The individual modular semiconductor processing units may be arranged together in various configurations to form cohesive processing units, each of which may be processed as a unit through various standard semiconductor processing tools.
The present invention provides a method for forming semiconductor devices by processing individual modular semiconductor processing units through various processing operations, while also providing for processing a cohesive processing unit formed of a group of individual modular semiconductor processing units, through various other processing operations, depending on the operation and the equipment used to perform the operation. The cohesive processing unit of individual modular semiconductor processing units may be arranged in accordance with the particular processing tool used to perform the particular operation. Test monitors may be added at various stages, and they may be removed after the conclusion of the particular operation, enabling the bulk of the group of individual modular semiconductor processing units to be processed on without delay. After the modular processing units are processed through a first processing operation, they may be arranged and processed as a group forming a cohesive processing unit, through another piece of semiconductor processing equipment adapted to process such a cohesive processing unit.
An aspect of the present invention is that highly integrated and advanced semiconductor devices may be formed on the modular semiconductor processing units, whether the modular semiconductor processing units are processed individually or simultaneously as part of a cohesive processing unit.